Lee Szuba About

Software Defined Radio


Lately I have been very interested in RF. I decided the perfect project to delve into radio was a software defined radio receiver (SDR), heavily inspired by Jeri Ellsworth’s videos on the topic.

From Jeri’s videos, I discovered Gerald Youngblood’s seminal articles and used these as a reference during my development. I have been using HDSDR as a quick and easy way to demodulate input signals and display a spectrum waterfall. I have also been experimenting with GNU Radio, eventually hoping to write drivers for my own custom hardware to run on the Raspberry Pi. The current FPGA code is available on GitHub.

The end goal of the project is to integrate a 130 Msps ADC (LTC2208), FPGA (Altera Cyclone IV), and Raspberry Pi into an integrated radio receiver, running GNU radio. The FPGA will downsample the signal, create the waterfall display, and pipe the data to the Pi through 10/100 Ethernet. The Pi will present the pre-processed waterfall to the user, as well as demodulate a narrower band signal (probably around 2 MHz bandwidth). Keeping the demodulation in the Pi will allow huge amounts of flexibility, but will take a significant amount of processing power. The Pi cannot possibly be presented with the full 60 MHz baseband, so this is where the FPGA comes in. This is a fairly lofty goal, but I am very excited to work on it. I expect it to be quite ongoing.

The first two versions of the radio used simple quadrature detectors and the computer sound card as an ADC. Version one used lower quality components and had a very high noise floor. Version two was an attempt to improve on the performance, but with a similar design.

Second Version

The second version of the SDR is again built around a quadrature sampling detector, with a similar coverage, but using a higher performance op amp (LT6231) and analog switch (ADG712) than the first version. Tuning is accomplished with a rotary encoder, which dynamically adjusts the Cyclone IV’s PLL.

The complete SDR set up (without computer)

Test Results

During the development of this version, I acquired a frequency counter and RF signal generator. This allowed me to perform further tests on the receiver.

Carrier Measurement

The first test was to inject a CW signal into the receiver. This checked basic functionality and distortion performance. The carrier was successfully observed with minimal mirroring in HDSDR.

Problems and Improvements


The tuning frequency steps are quite big (~0.5 MHz). This makes it tough to use in the shortwave band, as it is very easy to skip over the frequency you are interested in. The solution to this is to use an external PLL with better performance (fractional-n/sigma-delta), or to implement an NCO/DDS oscillator. Both of these methods are fairly complicated and difficult to implement. I may experiment with different types of all digital DDS or PLL solutions, but I am not yet sure of the direction I want to take. I may just wait for the direct sampling version and forget about the tuning altogether.

Overloading and Gain Compression

The presence of strong AM and FM broadcast stations has a tendency to overload the input of the receiver. This can cause the op amp after the detector to clip, creating intermodulation distortion and generally ruining the signal quality.

It also affects the input to the sound card, and requires lowering the gain, losing weaker signals in the process. This problem is fairly inherent in a wide bandwidth receiver. To mitigate this problem, a bandpass filter was designed and built for the 20 meter (14.1 MHz) band. The response before and after tuning is was measured. Before tuning, the different poles of the filter were at different frequencies creating a rather wide passband with a ‘lumpy’ response.

20 m band bandpass filter

Filter response before tuning

First Version

The first version of the SDR is a general coverage receiver, covering 100 kHz - ~50 MHz, using a computer sound card to digitize the baseband. It was very exciting to see the first radio signals come through! First AM radio, then shortwave SSB voice, and then CW (Morse Code). Watching the waterfall display in HDSDR is mesmerizing, and it gives insight into the radio spectrum.

It is built around a quadrature sampling mixer, using a 40XX analog switch, and LM324 op amp, built on proto-board. The clock source is a DE0 Nano FPGA development board, using the on board PLL.

Problems and Improvements

On this version, the tuning frequency was hard coded, so the FPGA needs to be re-flashed to change the tuning. This was obviously less than ideal. Unfortunately, the performance leaves to be desired as the noise performance of the op amp is very very poor. This version is just a proof of concept, to try and understand the hardware and how the sampling detector works. No real measurements were performed, as I did not have any of the required test equipment at the time. The hardware later failed, and I decided because of the poor performance it was not worth fixing. Work on an improved version began.